 Introduction |
| Fetch
Cycle |
| Execute
Cycle |
| Interrupt
Cycle |
| Modern
Processors |
| Glossary
of Terms |
At the grass roots of all modern processors is a process which has basically remained unchanged since the inception of computers, that of the instruction execution cycle.
Components
All computers can be summarized with just two basic components: (a) primary storage or memory and (b) a central processing unit or CPU. The CPU is the "brains" of the computer. Its function is to execute programs which are stored in memory. This procedure is accomplished by the CPU fetching an instruction stored in memory, then executing the retreived (fetched) instruction within the CPU before proceeding to fetch the next instruction from memory. This process continues until they are told to stop.
The following illustration (Figure 1) summarizes this continuous process of fetching and execution of instructions.
Figure 1: A simplified two step instruction cycle
What is the Instruction Execution Cycle?
All computers have an instruction execution cycle. A basic instruction execution cycle can be broken down into the following steps:
Each of these two steps will be discussed in greater detail in the following sections.
Although we have been concentrating on the CPU and memory, there are additional components in a computer such as the I/O modules which can interact with the processor. In an improved instruction execution cycle, we can introduce a third cycle known as the interrupt cycle. Figure 2 illustrates how the interrupt cycle fits into the overall cycle.
Figure 2: Instruction cycle with Interrupts (Stallings, 1995)
Fetch Cycle
To start off the fetch cycle, the address which is stored in the program counter (PC) is transferred to the memory address register (MAR). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the control unit (CU). To finish the cycle, the newly fetched instruction is transferred to the instruction register (IR) and unless told otherwise, the CU increments the PC to point to the next address location in memory.
Figure 3: An animated fetch cycle
The illustrated fetch cycle above (Figure 3) can be summarised by the following points:
- PC => MAR
- MAR => memory => MBR
- MBR => IR
- PC incremented
After the CPU has finished fetching an instruction, the CU checks the contents of the IR and determines which type of execution is to be carried out next. This process is known as the decoding phase. The instruction is now ready for the execution cycle.
Execute Cycle
Once an instruction has been loaded into the instruction register (IR), and the control unit (CU) has examined and decoded the fetched instruction and determined the required course of action to take, the execution cycle can commence. Unlike the fetch cycle and the interrupt cycle, both of which have a set instruction sequence, the execute cycle can comprise some complex operations (commonly called opcodes).
The actions within the execution cycle can be categorised into the following four groups:
- CPU - Memory: Data may be transferred from memory to the CPU or from the CPU to memory.
- CPU - I/O: Data may be transferred from an I/O module to the CPU or from the CPU to an I/O module.
- Data Processing: The CPU may perform some arithmetic or logic operation on data via the arithmetic-logic unit (ALU).
- Control: An instruction may specify that the sequence of operation may be altered. For example, the program counter (PC) may be updated with a new memory address to reflect that the next instruction fetched, should be read from this new location.
For simplicity reasons, the following examples (illustrated in Figure's 4 and 5) will deal with two operations that can occur. The [LOAD ACC, memory] and [ADD ACC, memory], both of which could be classified as memory reference instructions. Instructions which can be executed without leaving the CPU are referred to as non-memory reference instructions.
LOAD ACC, memory
This operation loads the accumulator (ACC) with data that is stored in the memory location specified in the instruction. The operation starts off by transferring the address portion of the instruction from the IR to the memory address register (MAR). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the CU. To finish the cycle, the newly fetched data is transferred to the ACC.
The illustrated LOAD operation (Figure 4) can be summarised in the following points:
- IR [address portion] => MAR
- MAR => memory => MBR
- MBR => ACC
Figure 4: Animated Execute Cycle [LOAD ACC, memory] operation
ADD ACC, memory
This operation adds the data stored in the ACC with data that is stored in the memory location specified in the instruction using the ALU. The operation starts off by transferring the address portion of the instruction from the IR to the MAR. The CPU then transfers the instruction located at the address stored in the MAR to the MBR via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the CU. Next, the ALU adds the data stored in the ACC and the MBR. To finish the cycle, the result of the addition operation is stored in the ACC for future use.
The illustrated ADD operation (Figure 5) can be summarised in the following points:
- IR [address portion] => MAR
- MAR => memory => MBR
- MBR + ACC => ALU
- ALU => ACC
Figure 5: Animated Execute Cycle [ADD ACC, memory] operation
After the execution cycle completes, if an interrupt is not dedected, the next instruction is fetched and the process starts all over again.
Interrupt Cycle
An interrupt can be described as a mechanism in which an I/O module etc., can break the normal sequential control of the central processing unit (CPU). Table 1 below, summarises the most common form of interrupts that the CPU can receive.
The main advantage of using interrupts is that the processor can be engaged in executing other instructions while the I/O modules connected to the computer are engaged in other operations.
| Program | Generated by some condition that occurs as a results of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute am illegal machine instruction, and reference outside a user's allowed memory space. |
| Timer | Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis. |
| I/O | Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions. |
| Hardware failure | Generated by a failure such as power failure or memory parity error. |
Table 1: Classes of Interrupts (Stallings, 1995)
Up until now we have dealt with the instruction execution cycle on the hardware level. When interrupts are introduced, the CPU and the operating system driving the system, is responsible for the suspension of the program currently being run, as well as restoring that program at the same point before the interrupt was detected. To handle this, an interrupt handler routine is executed. This interrupt handler is usually built into the operating system.
Before the interrupt handler routine can ran, several processes must occur first. A typical sequence of events is illustrated in Figure 6 below. After the completion of the interrupt handler routine, the normal sequencial fetch / execute cycle begins.
Figure 6: Sample interrupt processing (Stallings, 1995)
Modern Processors
When central processing units (CPU's) were first developed they processed the first instruction before starting the second. For example, the processor fetched the first instruction, decoded it, then executed the fetched instruction, before fetching the second instruction and starting the process over again (see Figure 7). In a processor, such as the one just described, the CPU itself is the weak link. The external bus operates for at least one cycle (clock pulse) in the three, but has to wait the remaining cycles for the CPU.
Note: Figures 7, 8, 9 and 10 have been adapted from Tredennick, 1996.
Figure 7: Instruction execution cycle in a non-pipelined processor
Modern processors on the other hand, have developed what are called pipelines. Pipelines are the most common implementation technique in a CPU today that increases the performance of the system. The idea behind the pipeline is that while the first instruction is being executed, the second instruction can be fetched, or in simple terms, instruction overlap.
The first pipelines to be introduced where a simple three-stage pipeline (see Figure 8). While this utilises all the resources of the system, conflict of resources can occur, resulting in instructions being held untill the previous instruction has completed its current stage. Apart from these minor hiccups, it is possible for the CPU to complete an instruction every cycle as opposed to the earlier processors which required three cycles per instruction.
Figure 8: Instruction execution cycle in a three-stage pipelined processor
Figure 9 illustrates what is known as an extended pipeline. To overcome the delays associated with the three stage pipeline, modern processors have broken down the execute cycle into a number of phases, some have even broken down the fetch cycle in the fight to overcome delays in their processors. No matter how many phases the cycle is broken down to, the end result is that only one instruction can be completed every cycle.
Figure 9: Instruction execution cycle in an extended-pipelined processor
Enter the world of superscalar pipeline, where more than one instruction can be issued per clock cycle. Intel describes their processors by different levels. For example a level 2 (L2) processor (Pentium) can issue two instructions per clock cycle and their level 3 (L3) processor (Pentium Pro) can issue 3. Figure 10 illustrates a level 2 superscalar pipelined processor. Other processors which are available today include Motorola's 68060 (L2) and DEC's Alpha 21164 chip (L4) to name a few.
Figure 10: Instruction execution cycle in a six-stage level 2 superscaler pipelined processor
Glossary of Terms
Accumulator (ACC)
A register located on the central processing unit. The contents can be used by the arithmetic-logic unit for arithmetic and logic operations, and by the memory buffer register. Usually, all results generated by the arithmetic-logic unit end up in the accumulator.
Arithmetic-Logic Unit (ALU)
Performs arithmetic operations such as addition and subtraction as well as logical operations such as AND, OR and NOT. Most operations require two operands. One of these operands usually comes from memory via the memory buffer register, while the other is the previously loaded value stored in the accumulator. The results of an arithmetic-logic unit operation is usually transfered to the accumulator.
Central Processing Unit (CPU)
The "brains" of the computer. The basic components found on the central processing unit include the accumulator, arithmetic-logic unit, control unit, instruction register, memory address register, memory buffer register and the program counter.
Clock Pulse
A circuit which sends pulses of current to the central processing unit. Nothing happens in the computer untill a pulse is received. The measurement of the number of clock pulses sent every second is expressed in megahertz (MHz), for example, a 100MHz computer sends 100 million pulses every second.
Control Unit (CU)
Circuitry located on the central processing unit which coordinates and controls all hardware. This is accomplished by using the contents of the instruction register to decide which circuits are to be activated.
Instruction Register (IR)
A register located on the central processing unit which holds the contents of the last instruction fetched. This instruction is now ready to be executed and is accessed by the control unit.
Memory
Memory is made up of a series of zero's (0) and one's (1) called bits or binary. These individual bits are grouped together in lots of eight and are referred to as a byte.Every byte in memory can be accessed by a unique address which identifies its location. The memory in modern computers contains millions of bytes and is often referred to as random-access memory (RAM).
Memory Address Register (MAR)
A register located on the central processing unit which is in turn connected to the address lines of the system. This register specifies the address in memory where information can be found and can be also used to point to a memory location where information is to be stored.
Memory Buffer Register (MBR)
A register located on the central processing unit which is in turn connected to the data lines of the system. The main purpose of this register is to act as an interface between the central processing unit and memory. When the appropriate signal is received by the control unit, the memory location stored in the memory address register is used to copy data from or to the memory buffer register.
Program Counter (PC)
Contains the memory address of the next instruction to be executed. The contents of the program counter are copied to the memory address register before an instruction is fetched from memory. At the completion of the fetched instruction, the control unit updates the program counter to point to the next instruction which is to be fetched.